1. Field of the Invention
The present invention relates to a vertical MOS transistor having a trench structure and a method of manufacturing the same.
2. Description of the Related Art
FIG. 2 illustrates a schematic sectional view of a conventional vertical MOS transistor having a trench structure. A semiconductor substrate is formed in which a first conductive type lightly doped layer 2 is epitaxially grown on a first conductive type heavily doped substrate 1 to be a drain region. Then, a second conductive type diffusion region 3 referred to as a body region is formed from a surface of the semiconductor substrate by impurity implantation and high temperature thermal treatment at 1000° C. or higher. Further, from the surface, a first conductive type heavily doped impurity region 7 to be a source region and a second conductive type heavily doped body contact region 8 for the purpose of fixing a potential of the body region by an ohmic contact are formed. Here, since a potential of the first conductive type source region 7 and a potential of the second conductive type body contact region 8 are usually the same, the regions are laid out so as to be in contact with each other at surfaces as shown in FIG. 2. Then, intermediate insulating films 9 are formed on the surfaces. A source electrode 15 formed in the contact hole 13 on the source region 7 and the body contact region 8 electrically connects the source region 7 and the body contact region 8 to each other. A silicon trench 4 is formed by etching a single crystalline silicon, to be an epitaxially grown layer, through the first conductive type source region 7. A gate insulating film 5 and a polycrystalline silicon 6 containing a high concentration of impurity serving as a gate electrode fill the silicon trench 4. Further, the first conductive type heavily doped substrate 1 on a rear side of the semiconductor substrate is connected to a drain metallic electrode 16. As the intermediate insulating film 9 is formed on the surface of the silicon gate electrode 6, the silicon gate electrode 6 and the source region 7 do not short.
The above structure can function as a vertical MOS transistor in which a current from a drain formed of the first conductive type heavily doped substrate 1 on the rear side and the first conductive type epitaxial region 2 to a source formed of the first conductive type heavily doped region 7 on a front side is controlled through the gate insulating film 5 on a side wall of the trench 4 by the gate electrode 6 buried in the trench 4. This method can accommodate both an N-channel MOS transistor and a P-channel MOS transistor by appropriately reversing the conductive types between an N type and a P type.
Further, the vertical MOS transistor having the trench structure is characteristic in that, since a channel is formed completely vertically, the transistor allows application of technologies for miniaturization in a flat surface direction. As a result of development in miniaturization technologies, the area occupied by a flat transistor has become smaller and in recent years, there is a tendency that the amount of a drain current flowing onto the element unit area has increased.
In reality, when forming a plurality of cross section constructions by folding, as shown in FIG. 2, there is achieved a MOS transistor having an optional driving capacity, increased channel width, and increased amount of drain current. A basic structure of such a vertical MOS transistor and a method of manufacturing the same are schematically disclosed in, for example, U.S. Pat. No. 4,767,722.
However, such a structure of a vertical MOS transistor and a method of manufacturing the same have the following problems.
First of all, since the contact hole 13 is formed so as to extend over the heavily doped source region 7 and the body contact region 8 when the contact hole 13 is formed, it is necessary to provide a large area of the contact hole 13 in consideration of a layout margin for deviation in alignment between both of the regions 7 and 8. In addition, in order to avoid electrical conduction between the gate electrode 6 and the source electrode 15, a space defined between the contact hole 13 and a pattern of the trench 4 needs to be set at intervals in consideration of the layout margin for deviation in alignment. Then, these settings become a cause for impeding scale down (shrink) of the vertical MOS transistor, and obstructs miniaturization, low cost promotion or enhancement of a driving ability.
Secondarily, as described above, in recent years, the vertical MOS transistor has a tendency to increase density of a flowing drain current due to scale down, and along with this tendency, a thickness of a deposited film made of metal has been increased from a viewpoint of enhancement of reliability and low resistance promotion.
In general, the source metal electrode 15 formed within the contact hole 13 so as to be located above the heavily doped source region 7 is formed by utilizing the sputtering method. However, since the metal coating property in an edge portion 17 of the contact hole 13 as shown in FIG. 2 is poor due to the anisotropy of the deposition, a thickness of the edge portion of the contact hole 13 becomes about half that of a flat portion, and becomes equal to or smaller than ⅓ of that of the flat portion when the worst comes to the worst in some cases. For this reason, in order to avoid concentration of a current on this edge portion, and disconnection and insufficient reliability due to the current concentration, it is necessary to form a thicker metal film. However, this causes not only a change for the worse of throughput and pattern processing accuracy, but also an increase in material cost.